library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity core_read_mux IS
  GENERIC (
            cores      : natural := 1
          );
  PORT( 
       clk                : IN std_logic;  
       
       -- sram grant
       grant              : IN std_logic;  
       grant_valid        : IN std_logic;
       -- sram bus
       sram_read_addr     : in std_logic_vector(17 DOWNTO 0);
       sram_read_valid    : IN std_logic;
       -- sram request
       request_sram      : out std_logic;
       request_addr      : out std_logic_vector(17 DOWNTO 0);
       -- cores request
       read_request_addr  : in std_logic_vector((cores*18)-1 downto 0); 
       start_schedule     : out  std_logic;
       schedule_nr        : in   std_logic_vector (cores-1 DOWNTO 0);
       scheduling_done    : in   std_logic           
    );
end core_read_mux;



architecture Behavioral of core_read_mux is
   
  signal addr_pointer : std_logic_vector(17 downto 0) := (others => '0');
   
  TYPE STATE_TYPE IS (
      idle,
      request,
      granted
   );
 
   SIGNAL state : STATE_TYPE := idle; 
    
begin
        

 
process (clk)
begin
  if rising_edge(clk) then
    
    
    case state is
    
      when idle =>
        if scheduling_done='1' then
          state <= request;
          addr_pointer <= read_request_addr(17 downto 0); ---- tooooooooooooodooooooooooooo
        end if; 
      
      when request =>
        if grant='1' and grant_valid='1' then
          state <= granted;
        end if;
        
      when granted =>
        if sram_read_valid='1' and addr_pointer=sram_read_addr then
          state <= idle;  
        end if;
	
    end case;
    
  end if;
end process;

  
  request_sram <= '1' when state=request else '0';
  request_addr <= addr_pointer;
  
  start_schedule <= '1' when state=idle and scheduling_done='1' else '0';


end Behavioral;























